;; -*- mode: asm -*-

#include <io-avr.h>

#if WITH_UNDERSCORES
#define _U(x) _##x
#else
#define _U(x) x
#endif

#if FLASHEND > 0x2000
#define VECTOR(label) jmp _U(label)
#else
#define VECTOR(label) rjmp _U(label)
#endif

	.section	.init
	.func	.start_of_init
..start_of_init:
	VECTOR(_init__)
#ifdef INT0_vect
	VECTOR(_interrupt0_)
#endif
#ifdef INT1_vect
	VECTOR(_interrupt1_)
#endif
#ifdef INT2_vect
	VECTOR(_interrupt2_)
#endif
#ifdef INT3_vect
	VECTOR(_interrupt3_)
#endif
#ifdef INT4_vect
	VECTOR(_interrupt4_)
#endif
#ifdef INT5_vect
	VECTOR(_interrupt5_)
#endif
#ifdef INT6_vect
	VECTOR(_interrupt6_)
#endif
#ifdef INT7_vect
	VECTOR(_interrupt7_)
#endif
#ifdef TIMER2_COMP_vect
	VECTOR(_output_compare2_)
#endif
#ifdef TIMER2_OVF_vect
	VECTOR(_overflow2_)
#endif
#ifdef TIMER1_CAPT_vect
	VECTOR(_input_capture1_)
#endif
#ifdef TIMER1_COMPA_vect
	VECTOR(_output_compare1a_)
#endif
#ifdef TIMER1_COMPB_vect
	VECTOR(_output_compare1b_)
#endif
#ifdef TIMER1_OVF_vect
	VECTOR(_overflow1_)
#endif
#ifdef TIMER0_COMP_vect
	VECTOR(_output_compare0_)
#endif
#ifdef TIMER0_OVF_vect
	VECTOR(_overflow0_)
#endif
#ifdef SPI_STC_vect
	VECTOR(_spi_)
#endif
#ifdef UART_RX_vect
	VECTOR(_uart_recv_)
#endif
#ifdef UART1_RX_vect
	VECTOR(_uart1_recv_)
#endif
#ifdef UART_UDRE_vect
	VECTOR(_uart_data_)
#endif
#ifdef UART1_UDRE_vect
	VECTOR(_uart1_data_)
#endif
#ifdef UART_TX_vect
	VECTOR(_uart_trans_)
#endif
#ifdef UART1_TX_vect
	VECTOR(_uart1_trans_)
#endif
#ifdef ADC_vect
	VECTOR(_adc_)
#endif
#ifdef EE_RDY_vect
	VECTOR(_eeprom_ready_)
#endif
#ifdef ANA_COMP_vect
	VECTOR(_comparator_)
#endif
	
_U(_init__):
	ldi	r30, lo8 (_etext); load the end of .text segment
	ldi	r31, hi8 (_etext); this is a start of .data image
	ldi	r26, 0x60	; load start of ram
	ldi	r27, 0
	ldi	r28, lo8 (_edata-0x60); load size of .data image
	ldi	r29, hi8 (_edata-0x60)
	sbiw	r28,0
	breq	2f
1:				; one time label
	lpm			; copy a .data image from FLASH to RAM
	adiw	r30, 1
	st	X+, r0
	sbiw	r28, 1
	brne	1b
2:
	;; avr-ld always put .bss after .data
	clr	r1
	ldi	r26, lo8(__bss_start)
	ldi	r27, hi8(__bss_start)
	ldi	r16, hi8(__bss_end)
	rjmp	1f
..clr_bss:
	st	X+,r1
1:	cpi	r26, lo8(__bss_end)
	cpc	r27, r16
	brne	.clr_bss

 /* out SREG, r1 */
    VECTOR(main)
	.endfunc
	
..section .text
	.func	.weaks		; stay avr-as happy with -gstabs
..weaks:
	.weak	_U(_interrupt0_)
	.weak	_U(_interrupt1_)
	.weak	_U(_interrupt2_)
	.weak	_U(_interrupt3_)
	.weak	_U(_interrupt4_)
	.weak	_U(_interrupt5_)
	.weak	_U(_interrupt6_)
	.weak	_U(_interrupt7_)
	.weak	_U(_output_compare2_)
	.weak	_U(_overflow2_)
	.weak	_U(_input_capture1_)
	.weak	_U(_output_compare1a_)
	.weak	_U(_output_compare1b_)
	.weak	_U(_overflow1_)
	.weak	_U(_output_compare0_)
	.weak	_U(_overflow0_)
	.weak	_U(_spi_)
	.weak	_U(_uart_recv_)
	.weak	_U(_uart1_recv_)
	.weak	_U(_uart_data_)
	.weak	_U(_uart1_data_)
	.weak	_U(_uart_trans_)
	.weak	_U(_uart1_trans_)
	.weak	_U(_adc_)
	.weak	_U(_eeprom_ready_)
	.weak	_U(_comparator_)

_U(_interrupt0_):
_U(_interrupt1_):
_U(_interrupt2_):
_U(_interrupt3_):
_U(_interrupt4_):
_U(_interrupt5_):
_U(_interrupt6_):
_U(_interrupt7_):
_U(_output_compare2_):
_U(_overflow2_):
_U(_input_capture1_):
_U(_output_compare1a_):
_U(_output_compare1b_):
_U(_overflow1_):
_U(_output_compare0_):
_U(_overflow0_):
_U(_spi_):
_U(_uart_recv_):
_U(_uart1_recv_):
_U(_uart_data_):
_U(_uart1_data_):
_U(_uart_trans_):
_U(_uart1_trans_):
_U(_adc_):
_U(_eeprom_ready_):
_U(_comparator_):
	reti